1. Field of the Invention
The present invention relates to a semiconductor package and fabricating method thereof.
2. Description of the Related Art
The semiconductor package is developing from DIP (Dual Inline Package) and PGA (Pin Grid Array) of plated-through package to QFP (Quad Flat Package) and SOP (Small Outline Package) of the SMT (Surface-mount technology) package in small size which has a superior electrical performance, then to TQFP (Thin Quad Flat Package) and TSOP (Thin Small Outline package). Since the middle of the 1990's, such a SMT package of light and thin is developed to the package of BGA (Ball Grid Array) type that has the strong points of the Solder Flip Chip and the SMT technology, it takes new heights of the package technology of new solder ball connection.
Since the latter half of the 1990's, the semiconductor package is developing to a CSP (Chip Scale Package) type which improves the size and electrical performance of the BGA (Ball Grid Array). The CSP technology is a high-density package in which chip size is over 80% of the package size, and the CSP technology is becoming necessary package part in the downsizing electronic products. The individual chip package is developing to the system package of MCM (Multi-Chip Module), SIP (System In Package) or SOP (System On Package) type.
However, it is very difficult to use the system package at high frequency, because the resistance component is large and the cross talk between wiring patterns is serious.
The technology for stacking a plurality of semiconductor chip is developing to solve such problems. The chip stack technology is capable of stacking logic chips and memory chips in the vertical direction so that various functions of semiconductor chips can be accumulated in a narrow space. However, it is difficult to use the chip stack technology in the area of high frequency since the conductive wire is used as the wire interconnection method.
Besides, a conventional connection mode of such as a wire bonding and TAB (Tape Automated Bonding) reached limits of improving the electrical function and reducing the system size. Therefore, a new interconnection technology of DCA (Direct Chip Attach) technology utilizing the through silicon via technology is now developing. Such a DCA technology in which the resistance or various parasitic capacitances is little and the cross talk phenomenon is rare because of shortness in the length of a signal line has a strong point, so that it is very easy to apply to the high frequency domain.
However, the DCA technology using through silicon via technology is difficult to form the through silicon via in the semiconductor chip, and to fill copper metal into the through silicon via, which brings the problem of reducing throughput. The semiconductor chip itself cracks since copper metal swells by the heat generated during the operation of the semiconductor chip.